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CXA3038N
IQ Detection IC for Digital Satellite Broadcast Tuner
Description The CXA3038N is an IC for IQ-detection of DSS, DVB, and other digital satellite broadcast QPSK modulation signals in the 480 MHz band. It consists of an AGC amplifier circuit, oscillator circuit, phase shifter circuit, and phase comparison circuit. In addition, the chip has a PLL circuit for frequency control and built-in control data. It realizes highaccuracy oscillator frequencies through use of a lowcost LC resonance circuit. Features * Built-in PLL for controlling oscillator frequency. * Oscillator frequency based at 479.5 MHz is adjustable in 4 steps of 50 kHz using the voltage of the control pin. * Reference OSC allows switching to 4 MHz or 10 MHz. * Built-in output buffer for reference OSC. * Low-impedance IQ output. * AGC gain variation 35 dB. Applications Digital satellite broadcast tuner Structure Bipolar silicon monolithic IC 24 pin SSOP (Plastic)
Absolute Maximum Ratings (Ta=25 C) * Supply voltage VCC -0.3 to 5.5 * Storage temperature Tstg -55 to +150 Operating Conditions * Supply voltage * Operating temperature
V C
VCC Topr
4.75 to 5.30 -25 to +75
V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E97650A84-TE
CXA3038N
Block Diagram and Pin Configuration
REFOUT
OSCGND
DGND
24
23
22
21
20
19
18
VC
17
16
15
14
13
Ref OSC
Buffer
Charge Pump
OSC
Prescaler 1/32
Divider 1/80, 1/200
Phase DET
Divider 10bit+4bit
Phase Shifter
Comparator DC AMP LPF QMIX Buffer
DC AMP
LPF
IMIX
Buffer AGC AMP
1
IQVCC
2
QOUT
3
XCONT
4
IOUT
5
IQGND
6
GND
7
RFGND
8
AGC
9
RFIN2
10
11
RFVCC
RFIN1
--2--
NSET
LOOUT
12
XTAL
OSC2
PSVCC
LOCK
LPF
OSC1
DVCC
CXA3038N
Pin Description Pin No. 1 Symbol IQVCC Typical pin voltage 5V
1
Equivalent circuit
Description IQ output circuit VCC.
20
2
QOUT
2.7 V
2
Q output.
5
21
3
XCONT
Open or 5 V when using 4 MHz crystal ; 0 V when using 10 MHz crystal.
10k 90k
3
20
Switching pin for reference divider frequency-division ratio. This is set to 80 frequency divisions when open or connected to VCC; 200 frequency divisions when connected to GND.
1
20
4
IOUT
2.7 V
4
I output.
5
5 6 7
IQGND GND RFGND
0V 0V 0V
11
IQ output circuit GND. GND. RF circuit (AGCAmp, MIXER) GND.
8
AGC
0 to 4 V
20k
8
20k
AGCAmp gain adjustment.
7
--3--
CXA3038N
Pin No.
Symbol
Typical pin voltage
9
10
Equivalent circuit
Description
9
RFIN2
2.1 V
5k
5k
RF signal inputs.
10
RFIN1
2.1 V
7
2.2V
11
RFVCC
5V
21
RF circuit (AGCAmp, MIXER, OSC) VCC.
12
NSET
1.6 V
12
OSC frequency fine-adjustment. The oscillator frequency based at 479.5 MHz is adjustable in 4 steps of 50 kHz by applying a voltage of 0 to 5 V.
20
14
13
LOOUT
4V
13 8k 20
Output for OSC frequency signal divided into 32 frequency divisions.
14
PSVCC
5V
VCC for 32 frequency division circuit. This is set to open when activating the built-in PLL.
11
15
OSC2
3.7 V
16 3p 15
700
700
3p
OSC pins. These pins connect the varicap diode and coil resonance circuit.
16
OSC1
3.7 V
17
17
OSCGND
0V
OSC circuit and phase shifter circuit GND.
--4--
CXA3038N
Pin No.
Symbol
Typical pin voltage
21
Equivalent circuit
Description
10k 100
18
VC
0.3 V to 5 V
18
Voltage output for varicap diode making up the VCO.
20
21
100
19
LPF
1.8 V to 3.7 V
19
Phase comparison output. This pin connects the loop filter.
20
20 21
DGND DVCC
0V 5V
21
PLL circuit GND. PLL circuit VCC.
22
REFOUT
4.1 V
22
REFOSC output.
20
21
23
LOCK
0.01 V when unlocked; 3.2 V when locked
23 200k 20
PLL lock/unlock monitor.
21 60k 20p 20p
24
XTAL
4.4 V
24
Crystal connection.
20
--5--
CXA3038N
Electrical Characteristics Circuit current Item Circuit current A Circuit current D Circuit current L
(Ta=25 C, VCC=5 V, see the Electrical Characteristics Measurement Circuit.) Measurement conditions Analog circuit current at no signal. Total current of IQVCC and RFVCC. PLL circuit current. DVCC current. 32-frequency division circuit current at no signal. PSVCC current. Min. 41 2 1.1 Typ. 60 3.5 1.6 Max. 80 5.5 2.4 Unit mA mA mA
Symbol ICCA ICCD ICCPS
AC Characteristics Item Input sensitivity Gain control range
(Ta=25 C, VCC=5 V, see the Electrical Characteristics Measurement Circuit.) Min. 32.5 52 Typ. -50 35 54 Max. -- 57 4 0.5 0.5 0.1 25 2.5 2.5 3 3 9 32 -88 -81 -21 -34 -40 -34 -40 -34 1.25 k 1.4 3.5 3.5 Unit dBm dB dB deg dB deg dB MHz Vp-p Vp-p dB dB dBc/Hz dB dBm dBm dBm dBm pF
Symbol Measurement conditions Iout=10 MHz, 1 Vp-p VIN GAGC Iout=10 MHz, 1 Vp-p, AGC=4 V-0 V RF=-50 dBm, Iout=10 MHz, AGC=4 V Conversion gain CG (Full gain) RF=-50 dBm, Iout=10 MHz, 1 Vp-p IQ phase error BP RF=-50 dBm, Iout=10 MHz, 1 Vp-p IQ amplitude error BV Phase frequency error fBP RF=-50 dBm, Iout=0 MHz-15 MHz, 1 Vp-p Amplitude frequency error fBV RF=-50 dBm, Iout=0 MHz-15 MHz, 1 Vp-p RF=-50 dBm, Iout=From 1 Vp-p to 3 dB down Cut-off frequency fC RF=-30 dBm, Qout=10 MHz, AGC=4 V VQMAX Maximum Q output (Full gain) RF=-30 dBm, Iout=10 MHz, AGC=4 V VIMAX Maximum I output (Full gain) NF Iout=10 MHz, AGC=4 V (Full gain), DSB Noise figure RF1=489.5 MHz, RF2=490.5 MHz, Third-order IM3 Iout=1 Vp-p intermodulation distortion RF=-50 dBm, Iout=10 MHz, 1Vp-p, Local oscillation CN 10 kHz offset phase noise RF=-50 dBm, Iout=10 MHz, 1Vp-p, refLK PLL reference leak 50 kHz S/I RF pin local oscillation leak QOUT pin local oscillation leak IOUT pin local oscillation leak REFout pin local oscillation leak RF input admittance RFLK QLK1 QLK2 ILK1 ILK2 AGC=4 V, f=479.5 MHz AGC=4 V, f=479.5 MHz AGC=0 V, f=479.5 MHz AGC=4 V, f=479.5 MHz AGC=0 V, f=479.5 MHz
REFLK f=479.5 MHz r C f=479.5 MHz, AGC=4 V (Full gain)
Measured value for untuned inputs. Noise figure is the direct reading value from the NF meter. --6--
CXA3038N
PLL Block
(Ta=25 C, VCC=5 V, see the Electrical Characteristics Measurement Circuit.) Min. Typ. -50 50 0.3 2.8 0 3.2 0.01 4.000 280 VCC 4.2 0.2 Max. Unit A A V V V MHz mVp-p
Item Symbol Measurement conditions LPF (charge pump) H output current ILPFH L output current ILPFL VC Output voltage range VVCH XCONT=OPEN, PLL lock LOCK H output voltage VLH XTAL=4 MHz, XCONT=OPEN, PLL lock XTAL=4 MHz, XCONT=GND, PLL unlock L output voltage VLL REFOUT Output frequency fREF XTAL=4 MHz Output amplitude VREF XTAL=4 MHz LOOUT (32 frequency divisions) OSC=479.5 MHz during PLL lock Output frequency fLO Output amplitude VLO OSC=479.5 MHz during PLL lock OSC control 479.7 MHz control voltage f+4 NSET=0 V, f0 V-f0=f4 479.65 MHz control voltage f+3 NSET=0.4 V, f0.4 V-f0=f3 479.6 MHz control voltage f+2 NSET=0.8 V, f0.8 V-f0=f2 479.55 MHz control voltage f+1 NSET=1.2 V, f1.2 V-f0=f1 479.5 MHz control voltage f0 NSET=1.6 V 479.45 MHz control voltage f-1 NSET=2.0 V, f2.0 V-f0=f-1 479.4 MHz control voltage f-2 NSET=2.4 V, f2.4 V-f0=f-2 479.35 MHz control voltage f-3 NSET=2.6 V, f2.6 V-f0=f-3 479.3 MHz control voltage f-4 NSET=3.2 V, f3.2 V-f0=f-4
230
400
300 0.597 VCC 0.517 VCC 0.438 VCC 0.358 VCC 0.279 VCC 0.199 VCC 0.120 VCC 0.042 VCC 0
14.9844 380
500 VCC 0.590 VCC 0.515 VCC 0.436 VCC 0.356 VCC 0.277 VCC 0.197 VCC 0.118 VCC 0.04 VCC
MHz mVp-p V V V V V V V V V
--7--
Electrical Characteristics Measurement Circuit
REFOUT LOOUT DVCC (+5V) PSVCC (+5V) VC
680n
L: Inductance constant Wire Winding Number diameter diameter of turns 0.5 3.0 2.5 LOCK
5p
XTAL
L 1T362
2p
1n
80nH
1n
10n 4MHz
10n
1n 23 22 21 20 19 18 17 16 15 14 13
24
XTAL
DVCC
LPF
VC
LOCK
DGND
OSC1
OSC2
51k
1n
PSVCC
REFOUT
IQVCC
IOUT
RFGND
RFIN1
QOUT
IQGND
AGC
RFVCC
XCONT
GND
RFIN2
1
2
3
4
5
6
7
1n
8
9
1n
10
11
12
1n
1n 100k XTAL XCONT 4MHz 5V/OPEN 10MHz GND
NSET
1n
1n
10
--8--
CXA3038N QOUT IOUT
AGC RF IN 1n
VCC (+5V)
OSCGND
LOOUT
10n
150n 51k
13k
CXA3038N
Application Circuit
REFOUT Reference Clock for Tuner stage PLL.
680n
5p
L 1T362
150n 51k L ; 0.5/3.0/2.5T
XTAL
2p
13k
1n
1n
15
10n 4MHz
10n
1n 23 22 21 20 19 18 17 16 14 13
24
XTAL
DVCC
LPF
VC
LOCK
DGND
OSC1
OSC2
51k PSVCC
80nH
REFOUT
IQVCC
IOUT
RFGND
RFIN1
QOUT
IQGND
AGC
RFVCC
XCONT
GND
RFIN2
1
2
3
4
5
6
7
1n
8
9
1n
10
11
12
1n
1n
VCC (+5V) 68k 33k
1n
10
1n
NSET
--9--
CXA3038N QOUT IOUT AGC
OSCGND
LOOUT
RF IN 479.5MHz from Tuner stage
CXA3038N
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXA3038N
Description of Operation (See the Electrical Characteristics Measurement Circuit.) Oscillator circuit * This is a differential amplification-type oscillator circuit, and it is oscillated by connecting an LC parallel resonance circuit via a coupling capacitance between Pin 15 and Pin 16. A varicap diode is used as a capacitor for the LC parallel resonance circuit to configure the VCO. Set the L value so that the OSC oscillation frequency is approximately 480 MHz when a voltage of 2.5 V is applied to the varicap diode. * The oscillator signal is injected into the phase shifter circuit. Phase shifter circuit * This is a phase shifter having CR configuration. This circuit produces two local signals having a 90 phase difference at 479.5 MHz and injects these signals to the IQ mixer circuit. AGC amplifier circuit * An IF signal (480 MHz band) from the tuner stage is input to Pins 9 and 10. This IF signal which is input to Pins 9 and 10 is amplified by the AGC amplifier and injected into the IQ mixer circuit. * The gain can be adjusted by applying the AGC voltage to Pin 8. The applied AGC voltage ranges from 0 to 4 V, with the minimum gain at 0 V and the maximum gain at 4 V. IQ mixer circuit * This is a double-balance mixer-type circuit consisting of two mixer circuits. * The IF signal amplified by the AGC amplifier is converted into a base band signal by the local signal. Low-pass filter circuit * This is a low-pass filter with a CR configuration. * The cut-off frequency is set at 25 MHz (-3 dB point). Output amplifier circuit * The signal is converted to a base band signal by the I and Q mixer circuits, and the high-frequency component is removed by the low-pass filter. This signal is then amplified by the output amplifier circuit and output to Pin 2 as a Q signal. In the same way, the I signal is output to Pin 4. * The output is low impedance.
--10--
CXA3038N
PLL circuit (when Pin 21 is connected to VCC) * A PLL is formed by connecting the anode of the LC parallel resonance circuit varicap diode to the Pin 18 output via a high resistance of approximately 10 k and connecting a loop filter between Pin 18 and Pin 19. * The PLL circuit consists of a main divider, reference divider, phase comparator, charge pump, and reference oscillator. * The frequency dividing data is included in the main divider, making external data settings unnecessary. * The reference frequency has been designed at 50 kHz. * Fine adjustment of the VCO frequency can be performed by changing the frequency dividing value of the main divider through an applied voltage to Pin 12. This allows adjustment in 4 steps at 50 kHz intervals based at 479.5 MHz as shown in the table below.
Pin 12 voltage [V] 0.597 VCC or more 0.517VCC to 0.595VCC 0.438VCC to 0.515VCC 0.358VCC to 0.436VCC 0.279VCC to 0.356VCC 0.199VCC to 0.277VCC 0.120VCC to 0.197VCC 0.042VCC to 0.118VCC 0 to 0.04VCC
Frequency dividing value 9594 9593 9592 9591 9590 9589 9588 9587 9586
VCO oscillation frequency [MHz] 479.70 479.65 479.60 479.55 479.50 479.45 479.40 479.35 479.30
* The reference divider has two types of frequency dividing data, 80 and 200. * Either 4 MHz or 10 MHz can be selected for the crystal oscillator. When using the 4 MHz crystal oscillator, opening Pin 3 will select a frequency dividing value of 80 for the reference divider, and the reference frequency will become 50 kHz. In the same way, when using the 10 MHz crystal oscillator, connecting Pin 3 to GND will select a frequency dividing value of 200 for the reference divider, and the reference frequency will become 50 kHz. This is summarized in the table below.
Crystal oscillator 4 MHz 10 MHz
Pin 3 voltage
Frequency dividing value of the reference divider Open 80 0.8 V or less 200
Reference frequency 50 kHz 50 kHz
--11--
CXA3038N
Reference oscillator circuit * This is oscillated by connecting a crystal oscillator (4 MHz or 10 MHz) between Pin 24 and GND. * The input capacitance of Pin 24 is approximately 14 pF. Therefore, a crystal with a load capacitance of 12 pF is recommended. When connecting a crystal with a large load capacitance of 16 pF or so, connect a low capacitance between Pin 24 and GND as shown in the figure below, and adjust the frequency.
24 Reference frequency fine-adjustment capacitance Capacitance of DC components eliminated Crystal oscillator 4MHz or 10MHz
* The reference oscillator signal is sent to the reference buffer circuit and output from Pin 22 by the emitter follower. The reference oscillator signal becomes the PLL comparison frequency in the IC. * The output amplitude is approximately 300 mVp-p.
200A 24 22
Usage as PLL reference frequency for the tuner block
Charge pump circuit
DVCC 1k From phase divider From main divider 1k 10k 19 100 18 50A 1k 500 20k 100
DGND
* The output current of the charge pump has been designed at 50 A. * The Pin 18 output voltage ranges from approximately 0.3 V to VCC. * In the loop filter example for the Electrical Characteristics Measurement Circuit, the lockup time is approximately 25 ms. --12--
CXA3038N
32 frequency division circuit (when Pin 14 is connected to VCC) * An oscillation signal is sent from the oscillator circuit to the 32 frequency division circuit via a coupling capacitance. The 32 frequency division signal is output from Pin 13 by the counter. * The output is approximately 400 mVp-p ECL output.
Notes on Operation * These circuits use high-frequency processes, and the electrostatic strength is weak. Therefore, please be careful of surges and other excessive input. * The IQ error may vary depending on the connection locations of the GND pattern and VCC-GND bypass capacitors, oscillation amplitude of the oscillator circuit, and other factors.
--13--
CXA3038N
RF input level vs. Phase difference IQ output frequency=1MHz, QOUT=1Vp-p 95 94 93 2 1.5 1
RF input level vs. Amplitude error IQ output frequency=1MHz, QOUT=1Vp-p
Phase difference [deg]
Amplitude error [dB]
RF input level [dBm] IQ output frequency vs. Phase difference RF input level=-40dBm, QOUT=1Vp-p
92 91 90 89 88 87 86 85 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10
0.5 0 -0.5 -1 -1.5 -2 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 RF input level [dBm] IQ output frequency vs. Amplitude error RF input level=-40dBm, QOUT=1Vp-p 2 1.5 1
95 94 93
Phase difference [deg]
Amplitude error [dB]
92 91 90 89 88 87 86 85 0 2 4 6 8 10 12 14 16 18 20
0.5 0 -0.5 -1 -1.5 -2
0
2
4
6
8
10
12
14
16
18
20
IQ output frequency [MHz] Supply voltage vs. Current consumption During PLL operation 90 35 30 25 70
IQ output frequency [MHz] Noise figure characteristics RF input level=-40dBm, QOUT=10MHz
80
Current consumption [mA]
60
NF [dB]
20 15 10
50
40
5 0 0
30 4.2
4.4
4.6
4.8
5
5.2
5.4
5.6
5.8
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Supply voltage [V]
AGC voltage [V]
--14--
CXA3038N
AGC voltage vs. Gain RF input level=-40dBm, IQ output frequency=1MHz 60 55 50
Third-order intermodulation distortion characteristics 20
10 Fundamental 0
QOUT output level [dBm]
45 40 35 30 25 20 15 10
-10
Gain [dB]
-20
-30
Third-order intermodulation distortion component
-40 OSC=479.5MHz RF1=498.5MHz RF2=490.5MHz AGC=4V 0
-50
0
1
2
3
4
5
-60 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 RF input level [dBm]
AGC voltage [V]
Phase noise characteristics RF input level=-40dBm, QOUT=1 MHz, 1Vp-p -50
-60
-70
C/N [dBc/Hz]
-80
-90
-100
-110
-120 0.1
1
10
100
1000
Offset frequency [kHz]
--15--
CXA3038N
Package Outline
Unit : mm
24PIN SSOP(PLASTIC)
+ 0.2 1.25 - 0.1 7.8 0.1 0.1 13
24
A
1 + 0.1 0.22 - 0.05
12 + 0.05 0.15 - 0.02 0.65 0.1 0.1
0.13 M
5.6 0.1
0 to 10 NOTE: Dimensions "" does not include mold protrusion. DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-24P-L01 SSOP024-P-0056 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.1g
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
--16--
0.5 0.2
7.6 0.2

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